In recent years, an individual identification technology using wireless communication (hereinafter, referred to as a wireless communication system) has attracted attention. In particular, as a data carrier which transmits/receives data by wireless communication, an individual identification technology with a wireless tag utilizing an RFID (radio frequency identification) technology (hereinafter, referred to as a wireless tag regardless of its shape such as a card shape or a chip shape) has attracted attention. A wireless tag is also referred to as an IC tag, an RFID tag, or an electronic tag.
In the field of manufacture and distribution, an individual identification technology with a wireless tag has started to be utilized for management of a large number of items and the like instead of conventional management with a bar code, and has been developed to be applied for individual identification.
Here, a wireless communication system refers to a communication system in which data is transmitted/received wirelessly between a transmitter receiver (also referred to as an interrogator), such as a reader/writer (hereinafter, referred to as a R/W), and a wireless tag. In such a wireless communication system, data which is to be transmitted and received is superposed on carrier waves emitted from the R/W, so that communication is performed.
As one function for improving reading accuracy and preventing collision, a wireless tag is equipped with a session flag. A session flag prevents additional readout of ID from the wireless tag from which the ID has been read out. For example, the session flag has two kinds of data of A and B and the wireless tag from which ID is read out is set from A to B.
The session flag has a persistence time regardless of electricity supplied from the R/W to the wireless tag. For example, when the session flag is once set to B, the session flag is set to B during a period shorter than the persistence time. The session flag is set to A during a period longer than the persistence time. A memory is needed for realizing the persistence time.
Memories used practically can be roughly classified into volatile memories and nonvolatile memories. Nonvolatile memories keep stored data regardless of presence or absence of supply of a power supply voltage. Volatile memories cannot keep stored data without supply of a power supply voltage.
As an example of volatile memories, DRAMs are given. FIG. 4 is a circuit diagram showing a structural example of a DRAM cell.
A memory cell 406 in FIG. 4 includes an n-channel transistor 401 and a capacitor 402. A gate of the n-channel transistor 401 is connected to a word line 405. One of a drain and a source of the n-channel transistor 401 is connected to the capacitor 402 and the other of the drain and the source of the n-channel transistor is connected to a bit line 404. A terminal of the capacitor 402 which is not connected to the n-channel transistor 401 is connected to a reference potential 403. Note that “connection” means “electrical connection” in this specification.
The n-channel transistor 401 is operated by the word line 405 at the time of writing and readout of data and is on at the time of the writing and readout of data. In addition, at the time other than the time of the writing and readout of data, the n-channel transistor 401 is off.
Presence or absence of electric charge in the capacitor 402, that is, a high voltage and a low voltage of a terminal voltage of the capacitor 402 correspond to binary data “1” and binary data “0”, respectively. Note that, in this specification, the high voltage refers to a voltage higher than the reference potential and the low voltage refer to a potential equal to the reference potential.
A voltage corresponding to the data “1” or the data “0” is applied from the bit line 404 to the capacitor 402 through the n-channel transistor 401, so that electricity is charged and discharged, and operation of writing is performed. Operation of readout is performed by detecting presence and absence of electric charge in the capacitor 402 and a high voltage and a low voltage. Electric charge kept in the capacitor 402 is output to the bit line, so that readout is performed. A sense amplifier which is not illustrated amplifies a minute change of the bit line 404, whereby the readout is performed.
Electric charge is accumulated in the capacitor 402, so that stored data is kept. However, leak of the electric charge kept in the capacitor 402 occurs due to various causes, so that a sufficient amount of the electric charge given in the capacitor 402 is to disappear eventually. That is, the stored data is crashed. A leakage current of the n-channel transistor 401 is a main cause of the leakage.
The data is read out before the electric charge disappears completely, and writing to the memory cell is performed again based on the data which is read out. If this cycle is repeated, the stored data can be kept for a long time. This operation is referred to as refresh operation.
In a circuit structure similar to that of the DRAM cell, if refresh operation is not performed, a period during which data can be kept is determined depending on the amount of electric charge in the capacitor and the leakage current of the transistor (e.g., see Patent Document 1).
[Reference]
[Patent Document 1] Japanese Published Patent Application No. H06-029488.